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1 ds05-11022-1e fujitsu semiconductor data sheet memory cmos 2 1m 8 bits synchronous dynamic ram mb81117822a-125/-100/-84/-67 cmos 2 banks of 1,048,576-words 8 bits synchronous dynamic random access memory n description the fujitsu mb81117822a is a cmos synchronous dynamic random access memory (sdram) containing 16,777,216 memory cells accessible in an 8-bit format. the mb81117822a features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. the mb81117822a sdram is designed to reduce the complexity of using a standard dynamic ram (dram) which requires many control signal timing constraints, and may improve data bandwidth of memory as much as 5 times more than a standard dram. the mb81117822a is ideally suited for laser printers, high resolution graphic adapters, accelerators and other applications where an extremely large memory and bandwidth are required and where a simple interface is needed. n product line & features parameter mb81117822a -125 -100 -84 -67 clock frequency 125 mhz max. 100 mhz max. 84 mhz max. 67 mhz max. burst mode cycle time 8 ns min. 10 ns min. 12 ns min. 15 ns min. ras access time 45 ns max. 54 ns max. 56 ns max. 60 ns max. cas access time 21 ns max. 24 ns max. 26 ns max. 30 ns max. access time from clock (cl = 3) 7.5 ns max. 8.5 ns max. 8.5 ns max. 9 ns max. operating current (two banks active) 140 ma max. 130 ma max. 120 ma max. 110 ma max. power down mode current 2 ma max. single +3.3 v supply 0.3 v tolerance lvttl compatible i/o 2 k refresh cycles every 32.8 ms dual bank operation byte control by dqm burst read/write operation and burst read/single write operation capability this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. programmable burst type, burst length, and cas latency auto-and self-refresh (every 16 m s) cke power down mode output enable and input data mask
2 mb81117822a-125/-100/-84/-67 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n package parameter symbol value unit voltage of v cc supply relative to v ss v cc , v ccq e0.5 to +4.6 v voltage at any pin relative to v ss v in , v out e0.5 to +4.6 v short circuit output current i out 50 ma power dissipation p d 1.3 w storage temperature t stg e55 to +125 c package and ordering information e 44-pin plastic (400 mil) tsop-ii, order as mb81117822a-xxxfn (2k refresh) marking side (fpt-44p-m18) (normal bend) plastic tsop package
3 mb81117822a-125/-100/-84/-67 n pin assignments and descriptions pin number symbol function 1, 5, 9, 22, 36, 40 v cc , v ccq supply voltage 4, 8, 37, 39, 41, 43, dq 0 to dq 7 data i/o 3, 7, 23, 38, 42, 44 v ss , v ssq * ground 10, 11, 30, 34, 35 n.c. no connection 12 we write enable 13 cas column address strobe 14 ras row address strobe 15 cs chip select 16 a 11 (ba) bank select 17 ap auto precharge enable 17, 18, 19, 20, 21, 24, 25, 26, 27, 28, 29 a 0 to a 10 address input row : a 0 to a 10 column : a 0 to a 8 31 cke clock enable 32 clk clock input 33 dqm input mask/output enable 1 2 3 4 5 9 10 6 7 8 13 14 15 16 17 18 19 20 21 22 26 25 24 23 38 37 36 35 34 33 32 31 30 29 11 28 12 27 44 43 42 41 40 39 cs a 11 a 10 /ap a 0 40-pin soj: ( top view ) v cc n.c. v ssq dq 1 v ccq dq 2 v ssq dq 3 v ccq n.c. n.c. we cas ras a 1 a 2 a 3 v cc v ss dq 7 v ssq dq 6 v ccq dq 5 v ssq dq 4 v ccq n.c. n.c. dqm clk cke n.c. a 9 a 8 a 7 a 6 a 5 a 4 v ss (making side) *: these pins are connected internally in the chip.
4 mb81117822a-125/-100/-84/-67 n block diagram fig. 1 e mb81117822a clk cke a 0 to a 11 , ap dqml dq 0 to dq 7 ras cas we cs bank-1 v ccq clock control signal mode column address ras cas we dram core col. addr. bank-0 i/o row addr. to each block v ss / v ssq command address buffer/ i/o data buffer/ v cc dqmu
5 mb81117822a-125/-100/-84/-67 n function truth table command truth table notes: *1. v = valid, l = logic low, h = logic high, x = either l or h. *2. all commands assumes no csus command on previous rising edge of clock. *3. all commands are assumed to be valid state transitions. *4. all inputs are latched on the rising edge of clock. *5. nop and desl commands have the same effect on the part. *6. bst command is effective only during full column burst read or write. *7. read, reada, writ, and writa commands should only be issued after the corresponding bank has been activated (actv command). refer to state diagram. *8. actv command should only be issued after corresponding bank has been precharged (pre or pall command). *9. required after power up. *10. mrs command should only be issued after all banks have been precharged (pre or pall command). refer to state diagram. function notes symbol cke cs ras cas we a 11 (ba) a 10 (ap) a 9 to a 8 a 7 to a 0 n-1 n device deselect *5 desl hxhxxxxx x x no operation *5 nop h x l h h h x x x x burst stop *6 bst h x l h h l x x x x read *7 read h x lhlhvl x v read with auto-precharge *7 reada h x lhlhvh x v write *7 writ h x l h l l v l x v write with auto-precharge *7 writa h x l h l l v h x v bank active (ras ) *8 actv h x l l h h v v v v precharge single bank pre h x l l h l v l x x precharge all banks pall h x l l h l x h x x mode register set *9,10 mrs h x llllvl v v
6 mb81117822a-125/-100/-84/-67 dqm truth table cke truth table notes: *1. the csus command requires that at least one bank is active. refer to state diagram. *2. ref and self commands should only be issued after all banks have been precharged (pre or pall command). refer to state diagram. *3. pd command should be issued after all banks have been precharged (pre or pall command). if a bank or all banks are in active state, pd command can be issued in conjuction with pre or pall command whichever precharge command makes all banks in idle state. function command cke dqm n-1 n data write/output enable enbl h x l data mask/output disable mask h x h current state function notes symbol cke cs ras cas we a 11 (ba) a 10 (ap) a 9 to a 0 n-1 n bank active clock suspend mode entry *1 csus h l xxxxxxx any clock suspend continue *1 llxxxxxxx clock suspend clock suspend mode exit lhxxxxxxx idle auto-refresh command *2 ref h h l l l h x x x idle self-refresh entry *2 self h l l l l h x x x self refresh self-refresh exit selfx lhlhhhxxx lhhxxxxxx idle power down entry pd hllhhhxxx hlhxxxxxx precharge power down entry pd hllhhhxxx hlhxxxxxx bank active power down entry *3 pd hlllhlvlx hlllhlxhx power down power down exit lhlhhhxxx lhhxxxxxx
7 mb81117822a-125/-100/-84/-67 operation command table (applicable to single bank) (continued) current state cs ras cas we addr command function notes idle h x x x x desl nop l h h h x nop nop l h h l x bst nop lhlh ba, ca, ap read/reada illegal l h l l ba, ca, ap writ/writa illegal l l h h ba, ra actv bank active after t rcd l l h l ba, ap pre/pall nop l l l h x ref/self auto-refresh or self-refresh *3 llll mode mrs mode register set (idle after t rsc )*3 bank active h x x x x desl nop l h h h x nop nop lhlh ba, ca, ap read/reada begin read: determine ap l h h l x bst nop l h l l ba, ca, ap writ/writa begin write: determine ap l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall precharge: determine precharge type l l l h x ref/self illegal llll mode mrs illegal
8 mb81117822a-125/-100/-84/-67 (continued) current state cs ras cas we addr command function notes read h x x x x desl nop (continue burst to end ? bank active) lhhh x nop nop (continue burst to end bank active) lhhl x bst burst stop bank active (bl = full column) nop (bl = 1, 2, 4, 8) lhlh ba, ca, ap read/reada terminate burst, new read ; determine ap l h l l ba, ca, ap writ/writa terminate burst, start write ; determine ap *4 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall terminate burst, precharge ; determine precharge type l l l h x ref/self illegal llll mode mrs illegal write h x x x x desl nop (continue burst to end write recovering) lhhh x nop nop (continue burst to end write recovering) lhhl x bst burst stop write recovering bank active (bl = full column) nop (bl = 1, 2, 4, 8) lhlh ba, ca, ap read/reada terminate burst, start read ; determine ap l h l l ba, ca, ap writ/writa terminate burst, new write ; determine ap *4 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall terminate burst, precharge ; determine precharge type *4 l l l h x ref/self illegal llll mode mrs illegal
9 mb81117822a-125/-100/-84/-67 (continued) current state cs ras cas we addr command function notes read with auto- precharge h x x x x desl nop (continue burst to end ? precharge) lhhh x nop nop (continue burst to end precharge) l h h l x bst illegal lhlh ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv other bank active, illegal on same bank *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal llll mode mrs illegal write with auto- precharge h x x x x desl nop (continue burst to end write recovering with precharge) lhhh x nop nop (continue burst to end write recovering with precharge) l h h l x bst illegal lhlh ba, ca, ap read/reada other bank active, illegal on same bank *2 l h l l ba, ca, ap writ/writa other bank active, illegal on same bank *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal llll mode mrs illegal
10 mb81117822a-125/-100/-84/-67 (continued) current state cs ras cas we addr command function notes precharge h x x x x desl nop (idle after t rp ) l h h h x nop nop (idle after t rp ) l h h l x bst illegal lhlh ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall nop (pall may affect other bank) *5 l l l h x ref/self illegal llll mode mrs illegal bank activating h x x x x desl nop (bank active after t rcd ) l h h h x nop nop (bank active after t rcd ) l h h l x bst nop (bank active after t rcd ) lhlh ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *6 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal llll mode mrs illegal
11 mb81117822a-125/-100/-84/-67 (continued) current state cs ras cas we addr command function notes write recovering h x x x x desl nop (bank active after t wr /t bwc ) l h h h x nop nop (bank active after t wr /t bwc ) l h h l x bst nop (bank active after t wr /t bwc ) lhlh ba, ca, ap read/reada start read; determine ap *4 l h l l ba, ca, ap writ/writa new write; determine ap l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal llll mode mrs illegal write recovering with auto- precharge h x x x x desl nop (precharge after t rwl /t bwl ) l h h h x nop nop (precharge after t rwl /t bwl ) l h h l x bst illegal lhlh ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal llll mode mrs illegal
12 mb81117822a-125/-100/-84/-67 (continued) abbreviations: current state cs ras cas we addr command function notes refreshing h x x x x desl nop (idle after t rc ) l h h x x nop/bst nop (idle after t rc ) lhlx x read/reada writ/writa illegal llhx x actv/ pre/pall illegal lllx x ref/self mrs illegal *6 mode register setting h x x x x desl nop (idle after t rsc ) l h h h x nop nop (idle after t rsc ) l h h l x bst illegal lhlx x read/reada writ/writa illegal llxx x actv pre/pall ref/self mrs illegal ra = row address ba = bank address ca = column address ap = auto precharge
13 mb81117822a-125/-100/-84/-67 command truth table for cke (continued) current state cke n-1 cke n cs ras cas we addr function notes self refresh h x h x x x x invalid l h h x x x x exit self refresh, idle after t rc l h l h h h x exit self refresh, idle after t rc lhlhlx x illegal l h l l x x x illegal l lxxxx x nop (maintain self refresh) self refresh recovery h h h x x x x idle after t rc h h l h h x x idle after t rc hhlhlx x illegal h h l l x x x illegal h l h x x x x begin clock suspend next cycle h l l h h x x begin clock suspend next cycle h l l h l x x illegal h l l l x x x illegal lhxxxx x exit clock suspend next cycle l lxxxx x maintain clock suspend
14 mb81117822a-125/-100/-84/-67 (continued) current state cke n-1 cke n cs ras cas we addr function notes power down hxxxxx ? inv alid lh hxxx x exit power down mode ? idle lhhh x l lxxxx x nop (maintain power down mode) l h l l x x x illegal lhlhlx x illegal both banks idle h h h x x x ? refer to the operation command table h h l h x x ? refer to the operation command table h h l l h x ? refer to the operation command table h h l l l h x auto-refresh hhllll special mode refer to the operation command table hhllll mode refer to the operation command table h l h x x x ? refer to the operation command table h l l h x x ? refer to the operation command table h l l h x x ? refer to the operation command table hllllh x self-refresh hlllll special mode refer to the operation command table hlllll mode refer to the operation command table lxxxxx x power down
15 mb81117822a-125/-100/-84/-67 (continued) notes: * 1. all entries assume the cke was high during the proceeding clock cycle and the current clock cycle. *2. illegal to bank in specited state; entry may be legal in the bank specited by ba, depending on the state of that bank. *3. illegal if any bank is not idle. *4. must satisfy bus contention, bus turn around, and/or write recovery requirements. *5. nop to bank precharging or in idle state. may precharge bank spesited by ba (and ap). *6. t rrd must be satisted for other bank. current state cke n-1 cke n cs ras cas we addr function notes bank active bank activeting read/write hxxxxx x refer to the operation command table lhxxxx x begin clock suspend next cycle l h x x x h x exit clock suspend next cycle lhxxxx x maintain clock suspend clock suspend hhxxxx x inv alid lhxxxx x exit clock suspend next cycle lhxxxx x maintain clock suspend any state other than listed above hhxxxx x refer to the operation command table hlxxxx x begin clock suspend next cycle lhxxxx x exit clock suspend next cycle l lxxxx x maintain clock suspend
16 mb81117822a-125/-100/-84/-67 clock latency or delay time for 2 bank operation notes: *1. assume opposite bank is in idle state. *2. assume opposite bank is in active state. *3. assume no i/o con?ict. *4. if t rp t ck , minimum latency is a sum of bl + cl. *5. assume pall command dose not affect any operation on opposite bank. *6. assume output is in high-z state. illegal command second command (opposite bank) mrs actv read reada wrt writa pre pall ref self first command mrs l mrd l mrd l mrd l mrd actv *1 t rrd *2 1 *2 1 *2 1 *2 11t ras read *1 1 *2 1 *2 1 *2 *3 1 *2 *3 111 reada *1 1 *2 1 *2 1 *2 *3 1 *2 *3 111 *1 *4 bl + t rp *1 *4 bl + t rp writ *1 1 *2 1 *2 1 *2 1 *2 111 writa *1 1 *2 1 *2 1 *2 1 *2 111 *1 bl + 1 + t rp *1 bl + 1 + t rp pre *1 t rp *1 1 *2 1 *2 1 *2 1 *2 111 *1 t rp *1 t rp *5 pall t rp *1 1 11 *1 *6 t rp *1 *6 t rp ref t rc t rc t rrd t rc self t pde + t rc t pde + t rc t pde + t rc t pde + t rc
17 mb81117822a-125/-100/-84/-67 mode register set self refresh idle read suspend bank active auto refresh power down bank active suspend fig. 2 e state diagram (simplited state diagram) write write suspend power on precharge read write with auto precharge read with auto precharge writ read read writ mrs self selfx ref actv cke cke\(pd) cke\ cke cke\ cke read writ reada writa reada* 1 cke\ cke writa pre or pall pre or pall power applied definition of allows manual input automatic sequence writa reada pre or pall pre or pall
18 mb81117822a-125/-100/-84/-67 n functional description sdram basic function three major differences between this sdram and conventional drams are: synchronized operation, burst mode, and mode register. the synchronized operation is the fundamental difference. an sdram uses a clock input for the synchronization, where the dram is basically asynchronous memory although it has been using two clocks, ras and cas . each operation of dram is determined by their timing phase differences while each operation of sdram is determined by commands and all operations are referenced to a positive clock edge. fig. 3 shows the basic timing diagram difference between sdrams and drams. the burst mode is a very high speed access mode utilizing an internal column address generator. once a column addresses for the trst access is set, following addresses are automatically generated by the internal column address counter. the mode register is to justify the sdram operation and function into desired system conditions. referenced in mode register table shows how sdram can be contgured for system requirement by mode register programming. clock (clk) and clock enable (cke) all input and output signals of sdram use register type buffers. a clk is used as a trigger for the register and internal burst counter increment. all inputs are latched by a positive edge of clk. all outputs are validated by the clk. cke is a high active clock enable signal. when cke = low is latched at a clock input during active cycle, the next clock will be internally masked. during idle state (all banks have been precharged.), cke = low enters the power down mode (standby) and this will make extremely low standby current. chip select (cs ) cs enables all commands inputs, ras , cas , and we , and address input. when cs is high, command signals are negated but internal operation such as burst cycle will not be suspended. if such a control isn?t needed, cs can be tied to ground level. command input (ras , cas and we ) unlike a conventional dram, ras , cas , and we do not directly imply sdram operation, such as row address strobe by ras . instead, each combination of ras , cas , and we input in conjunction with cs input at a rising edge of the clk determines sdram operation. refer to function truth table in page 5. address input (a 0 to a 10 ) address input selects an arbitrary location of a total of 1,048,576 words of each memory cell matrix. a total of twenty address input signals are required to decode such a matrix. sdram adopts an address multiplexer in order to reduce the pin count of the address line. at a bank active command (actv), eleven row addresses are initially latched and the remainder of eight column addresses are then latched by a column address strobe command of either a read command (read or reada) or write command (writ or writa). bank select (a 11 ) this sdram has two banks and each bank is organized as 1m words by 8-bit. bank selection by a 11 occurs at bank active command (actv) followed by read (read or reada), write (writ or writa), and precharge command (pre). data input and output (dq 0 to dq 7 ) input data is latched and written into memory at the clock followed by a write command input. data output is obtained by the following conditions followed by a read command input: t rac : from the bank active command when t rcd (min) is satisted. (this parameter is reference only.) t cac : from the read command when t rcd is greater than t rcd (min). t ac : from the clock edge after t rac and t cac . the polarity of the output data is identical to that of the input. data is valid between access time (determined by the three conditions above) and the next positive clock edge (t oh ).
19 mb81117822a-125/-100/-84/-67 data i/o mask (dqm) dqm is an active high enable input and has an output disable and inputs mask function. during burst cycle and when dqm = high is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst type. burst mode operation and burst type the burst mode provides faster memory access. the burst mode is implemented by keeping the same row address and by automatic strobing column address. access time and cycle time of burst mode is specited as t ac and t ck , respectively. the internal column address counter operation is determined by a mode register which detnes burst type and burst count length of 1,2 or 4 bits of boundary. in order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required: the burst type can be selected either sequential or interleave mode if burst length is 2 or 4. the sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns+1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least signitcant address(= 0). the interleave mode is a scrambled decoding scheme for a 0 and a 2 . if the trst access of column address is even (0), the next address will be odd (1), or vice-versa. current stage next stage method (assert the following command) burst read burst read read command burst read burst write 1st step mask command (normally 3 clock cycles) 2nd step write command after l owd burst write burst write write command burst write burst read read command burst read precharge precharge command burst write precharge precharge command
20 mb81117822a-125/-100/-84/-67 burst mode operation and burst type (continued) when the full burst operation is executed at single write mode, auto-precharge command is valid only at write operation. the burst type can be selected either sequential or interleave mode. but only the sequential mode is usable to the full column burst. the sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least signitcant address (= 0). full column burst and burst stop command (bst) the full column burst is an option of burst length and available only at sequential mode of burst type. this full column burst mode is repeatedly access to the same column. if burst mode reaches end of column address, then it wraps round to trst column address (= 0) and continues to count until interrupted by the news read (read)/write (writ/bwrit), precharge (pre), or burst stop (bst) command. the selection of auto-precharge option is illegal during the full column burst operation except write command at burst read & single write mode. the bst command is applicable to terminated the full column burst operation and illegal during the burst operation with length of 1, 2, 4, and 8. if the bst command is asserted during the full column burst mode, its operation is terminted immediately and the internal state moves to bank active. when read mode is interrupted by bst command, the output will be in high-z. for the detail rule, please refer to timing diagram-8. when write mode is interrupted by bst command, the data to be applied at the same time with bst command will be ignored. burst read & single write the burst read and single write mode provides single word write operation regardless of its burst length. in this mode, burst read operation does not be affected by this mode. burst length stating column address a 2 a 1 a 0 sequential mode interleave 2 x x 0 0 e 1 0 e 1 x x 1 1 e 0 1 e 0 4 x 0 0 0 e 1 e 2 e 3 0 e 1 e 2 e 3 x 0 1 1 e 2 e 3 e 0 1 e 0 e 3 e 2 x 1 0 2 e 3 e 0 e 1 2 e 3 e 0 e 1 x 1 1 3 e 0 e 1 e 2 3 e 2 e 1 e 0 8 0 0 0 0 e 1 e 2 e 3 e 4 e 5 e 6 e 7 0 e 1 e 2 e 3 e 4 e 5 e 6 e 7 0 0 1 1 e 2 e 3 e 4 e 5 e 6 e 7 e 0 1 e 0 e 3 e 2 e 5 e 4 e 7 e 6 0 1 0 2 e 3 e 4 e 5 e 6 e 7 e 0 e 1 2 e 3 e 0 e 1 e 6 e 7 e 4 e 5 0 1 1 3 e 4 e 5 e 6 e 7 e 0 e 1 e 2 3 e 2 e 1 e 0 e 7 e 6 e 5 e 4 1 0 0 4 e 5 e 6 e 7 e 0 e 1 e 2 e 3 4 e 5 e 6 e 7 e 0 e 1 e 2 e 3 1 0 1 5 e 6 e 7 e 0 e 1 e 2 e 3 e 4 5 e 4 e 7 e 6 e 1 e 0 e 3 e 2 1 1 0 6 e 7 e 0 e 1 e 2 e 3 e 4 e 5 6 e 7 e 4 e 5 e 2 e 3 e 0 e 1 1 1 1 7 e 0 e 1 e 2 e 3 e 4 e 5 e 6 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0
21 mb81117822a-125/-100/-84/-67 precharge and precharge option (pre, pall) sdram memory core is the same as drams?, requiring precharge and refresh operations. precharge rewrites the bit line and to reset the internal row address line and is executed by precharge command (pre). with the precharge command, sdram will automatically be in standby state after precharge time (t rp ). the precharged bank is selected by combination of ap and a 11 when precharge command is asserted. if ap = high, both banks are precharged regardless of a 11 (pall). if ap = low, a bank to be selected by a 11 is precharged (pre). the auto-precharge enters precharge mode at the end of burst mode of read or write without precharge command assertion. this auto precharge is entered by ap = high when a read or write command is asserted. refer to function truth table. auto-refresh (ref) auto-refresh uses the internal refresh address counter. the sdram auto-refresh command (ref) generates precharge command internally. all banks of sdram should be precharged prior to the auto-refresh command. the auto-refresh command should also be asserted every 16 m s or a total 2,048 refresh commands within a 32.8 ms period. self-refresh entry (self) self-refresh function provides automatic refresh by an internal timer as well as auto-refresh and will continue the refresh function until cancelled by selfx. the self-refresh is entered by applying an auto-refresh command in conjunction with cke = low (self). once sdram enters the self-refresh mode, all inputs except for cke will be don?t care (either logic high or low level state) and outputs will be in a high-z state. during a self-refresh mode, cke = low should be maintained. self command should only be issued after last read data has been appeared on dq. self-refresh exit (selfx) to exit self-refresh mode, apply minimum 4 clock cycle before cke brought high, and then the nop command (nop) or deselect command (desl) should be asserted within one t rc period. cke should be held high within one t rc period after t pde . refer to timing diagram for the detail. it is recommended to assert an auto-refresh command just after the t rc period to avoid the violation of refresh period. mode register set (mrs) the mode register of sdram provides a variety of different operations. the register consists of four operation telds; burst length, burst type, cas latency, and operation code. refer to mode register table in page 32. the mode register can be programmed by the mode register set command (mrs). each teld is set by the address line. once a mode register is programmed, the contents of the register will be held until re-programmed by another mrs command (or part loses power). mrs command should only be issued on condition that all dq is in high-z. the condition of the mode register is undetned after the power-up stage. it is required to set each teld after initialization of sdram. refer to power-up initialization below. power-up initialization the sdram internal condition after power-up will be undetned. it is required to follow the following power on sequence to execute read or write operation. 1. apply power and start clock. attempt to maintain either nop or desl command at the input. 2. maintain stable power, stable clock, and nop condition for a minimum of 200 m s. 3. precharge all banks by precharge (pre) or precharge all command (pall). 4. assert minimum of 8 auto-refresh command (ref). 5. program the mode register by mode register set command (mrs). in addition, it is recommended dqm and cke to track v cc to insure that output is high-z state. the mode register set command (mrs) can be set before 8 auto-refresh command (ref).
22 mb81117822a-125/-100/-84/-67 fig. 3 e basic timing for conventional dram vs synchronous dynamic ram ras cas dq clk cs dq t si ras cas cke we cas latency = 1 burst length = 4 active read/write precharge address hh h ba (a 11 ) ca ba (a 11 ) ra ba (a 11 ) ap (a 10 ) row address select column address select precharge t hi h : read l : write
23 mb81117822a-125/-100/-84/-67 n capacitance (t a = 25 c, f = 1 mhz) n recommended operating conditions (referenced to v ss ) notes: *1. overshoot limit : v ih (max) = tbd. *2. undershoot limit : v il (min) = e1.5 v with a pulsewidth 5 ns. parameter symbol typ. max. unit input capacitance, address c in1 ?4pf input capacitance, except for address c in2 ?4pf i/o capacitance c i/o ?7pf parameter notes symbol min. typ. max. unit supply voltage v cc , v ccq 3.0 3.3 3.6 v v ss , v ssq 000v input high voltage *1 v ih 2.0 ? v cc + 0.5 v input low voltage *2 v il e0.5 ? 0.8 v ambient temperature t a 0?70 c
24 mb81117822a-125/-100/-84/-67 n dc characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2 (continued) parameter symbol condition value unit min. max. output high voltage v oh(dc) i oh = e2 ma 2.4 ? v output low voltage v ol(dc) i ol = 2 ma ? 0.4 v input leakage current (any input) i li 0 v v in v cc ; all other pins not under test = 0 v e10 10 m a output leakage current i lo 0 v v in v cc ; data out disabled e10 10 m a operating current (average power supply current) mb81117822a-125 i cc1s no burst ; t ck = min t rc = min one bank active 0 v v in v cc ? 90 ma mb81117822a-100 85 MB81117822A-84 80 mb81117822a-67 75 mb81117822a-125 i cc1d no burst ; t ck = min t rc = min all banks active 0 v v in v cc ? ma mb81117822a-100 MB81117822A-84 ma mb81117822a-67 precharge standby current (power supply current) i cc2p cke = v il all banks idle t ck = min power down mode 0 v v in v cc ?2ma i cc2n cke = v ih all banks idle t ck = min 0 v v in v cc ?30ma active standby current (power supply current) i cc3p cke = v il any bank active t ck = min 0 v v in v cc ?30ma i cc3n cke = v ih any bank active t ck = min 0 v v in v cc ?50ma burst mode current (average powr supply current) mb81117822a-125 i cc4 t ck = min 0 v v in v cc ? ma mb81117822a-100 MB81117822A-84 ? mb81117822a-67 140 130 120 110 150 135 125 115
25 mb81117822a-125/-100/-84/-67 (continued) parameter symbol condition value unit min. max. refresh current #1 (average power supply current) mb81117822a-125 i cc5 auto-refresh ; t ck = min t rc = min t rrd = min 0 v v in v cc ?ma mb81117822a-100 MB81117822A-84 mb81117822a-67 refresh current #2 (average power supply current) i cc6 self-refresh ; cke = v il 0 v v in v cc ?2ma 120 110 100 90
26 mb81117822a-125/-100/-84/-67 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 2, 3, 4 parameter notes sym- bol mb81117822a -125 mb81117822a -100 mb81117822a -84 mb81117822a -67 unit min. max. min. max. min. max. min. max. clock period cas latency = 2 t ck 12 ? 15 ? 17 ? 20 ? ns cas latency = 3 8 10 12 15 ns clock high time t ch 3.5?4?4?4?ns clock low time t cl 3.5?4?4?4?ns input set up time t si 3?3?3?3?ns input hold time t hi 1?1?1?1?ns acess time from clock (t ck = min) *5,6 cas latency = 2 t ac ? 9 ? 9 ? 9 ? ns cas latency = 3 7.5 8.5 8.5 ns output in low-z t olz 2?3?3?3?ns output in high-z *7 t ohz 2?3?3?3?ns output hold time t oh 2?3?3?3?ns time between refresh t ref ? 32.8 ? 32.8 ? 32.8 ? 32.8 ms transition time t t 0.5 2 0.5 2 0.5 2 0.5 2 ns power down exit time t pde 3?3?4?5?ns 10 9
27 mb81117822a-125/-100/-84/-67 base values for clock count / latency clock count formula note 13 parameter notes sym- bol mb81117822a -125 mb81117822a -100 mb81117822a -84 mb81117822a -67 unit min. max. min. max. min. max. min. max. ras cycle time *8 t rc 75 ? 90 ? 100 ? 110 ? ns ras access time *9 t rac ?45?54?56?60ns cas access time *10,13 t cac ?21?24?26?30ns ras precharge time t rp 27?30?35?40?ns ras active time t ras 48 100000 60 100000 65 100000 70 100000 ns ras to cas delay time *11 t rcd 24?30?30?30?ns write recovery t wr 8 ?10?12?15?ns write to precharge delay time t rwl 8 ?10?12?15?ns ras to ras bank active delay time t rrd 24?30?30?30?ns clock 3 (round off a whole number) base value clock period
28 mb81117822a-125/-100/-84/-67 latency-fixed values (the latency values on these parameters are txed regardless of clock period.) notes: *1. i cc depends on the output termination or load conditions, clock cycle rate, and signal clocking rate; the specited values are obtained with the output open and no termination register. *2. an initial pause (desl or nop) of 200 m s is required after power-up followed by a minimum of eight auto refresh cycles. *3. ac characteristics assume t t = 1 ns and 30 pf of capacitive load. *4. 1.4 v is the reference level for measuring timing of input signals. transition times are measured between v ih (min) and v il (max). *5. assumes t rcd and t cac are satisted. *6. t ac also specites the access time at burst mode except for trst access. *7. specited where output buffer is no longer driven. *8. actual clock count of t rc (l rc ) will be sum of clock count of t ras (l ras ) and t rp (l rp ). *9. t rac is a reference value. maximum value is obtained from the sum of t rcd (min) and t cac (max). *10. assumes t rac and t ac are satisted. *11. operation within the t rcd (min) ensures that t rac can be met; if t rcd is greater than the specited t rcd (min), access time is determined by t cac or t ac . *12. all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *13. the t cac is programmed by the mode register. parameter notes sym- bol mb81117822a -125 mb81117822a -100 mb81117822a -87 mb81117822a -67 unit cke to clock disable l cke 1111 cycle dqm to output in high-z l dqz 2222 cycle dqm to input data delay l dqd 0000 cycle last output to write command delay l owd 2222 cycle write command to input data delay l dwd 0000 cycle precharge to output in high-z delay cl = 2 l roh 2222 cycle cl = 3 3333 cycle burst stop command to output in high-z delay cl = 2 l bsh 2222 cycle cl = 3 3333 cycle mode register access to bank active l mrd 2222 cycle cas to cas delay (min) l ccd 1111 cycle cas bank delay (min) l cbd 1111 cycle
29 mb81117822a-125/-100/-84/-67 output note: ac characteristics are measured in this condition. this load circuits are not applicable for v oh and v ol . fig. 4 e example of ac test load circuit r1 = 500 w cl = 50 pf lvttl 1.4 v
30 mb81117822a-125/-100/-84/-67 t si t hi t ch t ck t ac t hz t oh t lz t cl clk input (control, add. & data) output 2.0 v 1.4 v 0.8 v 1.4 v 2.0 v 0.8 v 1.4 v 2.4 v 0.4 v note: reference level of input signal is 1.4 v for lvttl. access time is measured at 1.4 v for lvttl. fig. 5 e timing diagram, setup, hold and delay time clk cke t pde (min) nop don?t care don?t care command 1 clock (min) nop actv fig. 6 e timing diagram, delay time for power down exit
31 mb81117822a-125/-100/-84/-67 fig. 7 e timing diagram, pulse width t pde , t rp , t ras , t rcd , t rwl , t rrd command command clk input (control) note: this parameter is a limit value of the rising edge of the clock from one command input to next input. t pde is the latency value from the rising edge of cke. measurement refrence voltage is 1.4 v. fig. 8 e timing diagram, access time t rac t cac t ac clk ras cas dq (output) t rcd q(valid) (cas latency e 1) t ck note: t rac is a reference value. data can be obtained after both t cac and t ac are satis?d.
32 mb81117822a-125/-100/-84/-67 n mode register table a 2 a 1 a 0 burst length 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 2 4 8 reserved reserved reserved full column 0 1 0 1 0 1 0 1 1 2 4 8 reserved reserved reserved reserved bt = 0 bt = 1 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 address op- code 0 0 cl bt bl mode register a 3 burst type sequential (wrap round, binary-up) interleave (wrap round, binary-up 0 1 a 6 a 5 a 4 cas latency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 mode register set a 9 op-code burst read & burst write burst read & single write 0 1 reserved 1 2 3 reserved reserved reserved reserved note: when a 9 = 1, burst length at write is always one regardless of bl value. a 1 a 0 00
33 mb81117822a-125/-100/-84/-67 timing diagram e 1 : clock enable - read and write suspend (@ bl = 4) q1 q2 (no change) q3 (no change) q4 d1 not written d2 not written d3 d4 clk cke clk (internal) dq (read) dq (write) notes: 1. the latency of cke (l cke ) is one clock. 2. during read mode, burst counter will not be incremented at the next clock of csus command. output remain the same data. 3. during the write mode, data at the next clock of csus command is ignored. 1 33 1 22 22 i cke (1 clock) i cke (1 clock) timing diagram e 2 : clock enable - power down entry and exit nop pd(nop) don?t care nop actv clk cke command 1 clock (min) 1 23 nop 3 notes: 1. precharge command (pre or pall) should be asserted if any bank is active and in the burst mode. 2. precharge command can be posted in conjunction with cke when burst mode is ended at this clock. 3. the actv command can be latched after t pde (min) + 1 clock (min). it is recommended to apply nop command in conjunction with cke. it is also recommended to apply minimum of 4 clocks to stabilize external clock prior to actv command. t pde t ref (max)
34 mb81117822a-125/-100/-84/-67 timing diagram e 3 : column address to column address input delay clk ras cas row address column address address column address column address column address i ccd (1 clock) column address t rcd (min) note: cas to cas address delay can be one or more clock period. i ccd i ccd i ccd timing diagram e 4 : different bank address input delay t rcd (min) t rrd (min) clk ras cas row address row address address column address column address column address bank 0 bank 1 bank 1 bank 1 bank 0 bank 0 a 11 (ba) column address t rcd (min) i cbd i cbd
35 mb81117822a-125/-100/-84/-67 timing diagram e 5 : dqm - input mask and output disable (@ bl = 4) clk dqm (@ read) dq (@ read) dqm (@ write) dq (@ write) q1 q2 hi-z q4 end of burst d1 masked d3 d4 end of burst i dqz (2 clocks) i dqd (same clock) timing diagram e 6 : precharge timing (applied to the same bank) t ras (min) clk command actv acvtm precharge
36 mb81117822a-125/-100/-84/-67 timing diagram e 7 : read interrupted by precharge (example @ cl = 2, bl = 4) clk command dq command dq command dq command dq hi-z q1 precharge precharge precharge precharge q1 q2 q1 q2 q3 q1 q2 q3 q4 hi-z hi-z no effect (end of burst) note: in case of cl = 2, the l roh are 2 clock. in case of cl = 3, the l roh are 3 clock. i roh (2 clocks) i roh (2 clocks) i roh (2 clocks)
37 mb81117822a-125/-100/-84/-67 timing diagram e 8 : read interrupted by burst stop (example @ bl = full column) clk command (cl = 2) dq command (cl = 3) dq q n q n+1 hi-z hi-z q n+2 q ne1 q ne2 q n q n+1 q ne1 q ne2 l bsh (2 clocks) l bsh (3 clocks) bst bst note: the bst command is applicable to terminated the full column burst operation. the selection of auto-precharge option is illegal during the full column burst operation except write command at burst read & single write mode. timing diagram e 9 : write interrupted by burst stop (example @ cl = 2) clk command dq last data-in masked by bst bst read t wr (min) note: the burst stop command is applicable only to full column burst operation.
38 mb81117822a-125/-100/-84/-67 timing diagram e 10 : write interrupted by precharge (example @ cl = 3) t rp (min) t rwl (min) clk command dq data-in last data-in masked by pre note: the precharge command (pre) should only be issued after the t rwl of tnal data input is satisted. actv precharge timing diagram e 11 : read interrupted by write (example @ cl = 3, bl = 4) clk command dqm dq data out masked data in data in note 1 note 2 note 3 write read notes: 1. first dqm makes high-impedance state high-z between last output and trst input data. 2. second dqm makes internal output data mask to avoid bus contention. 3. third dqm in illustrated above also makes internal output data mask. if burst read ends (tnal data output) at or after the second clock of burst write, this third dqm is required to avoid internal bus contention. i dwd (same clock) i owd (2 clocks) i dqz (2 clocks)
39 mb81117822a-125/-100/-84/-67 timing diagram e 12 : write to read timing (example @ cl = 3, bl = 4) clk command dq dqm note: read command should be issued after t wr of tnal data input is satisted if read command is applied to the same bank. write read d1 q1 q2 d3 masked by read t wr (min) d2 t cac (min) reada actv nop or desl actv q1 q2 t ras (min) 2 clocks (same value as cl) t rp (min) timing diagram e 13 : read with auto-precharge (example @ cl = 2, bl = 2 applied to same bank) clk command dqm dq note: precharge at read with auto-precharge command (reada) is started from number of clocks that is the same as cas latency (cl) after reada command is asserted.
40 mb81117822a-125/-100/-84/-67 timing diagram e 14 : write with auto-precharge (example @ cl = 2, bl = 2 applied to same bank) clk command dqm dq note: precharge at write with auto-precharge is started after the t rwl from the end of burst. even if the tnal data is masked by dqm, the precharge does not start the clock of tnal data input. once auto-precharge command is asserted, no new command within the same bank can be issued. auto-precharge command doesn?t affect at full column burst operation except burst read & single write mode. writa actv nop or desl actv t ras (min) e t rwl (min) d1 d2 t rwl (min) + t rp (min) timing diagram e 15 : auto-refresh timing t rc (min) t rc (min) t rrd (min) clk command a 11 (ba) ref command nop don?t care don?t care ba 1 nop nop ref nop 4 don?t care notes: 1. all banks should be precharged prior to the trst auto-refresh command (ref). 2. bank select is ignored at ref command. the refresh address is selected by internal refresh counter, and both banks are internally selected simultaneously. 3. either nop or desl command should be asserted during t rc period while auto-refresh mode. 4. any activation command such as actv or mrs command other than ref command should be asserted after t rc from the last ref command. 3
41 mb81117822a-125/-100/-84/-67 timing diagram e 16 : self-refresh entry and exit timing t rc (min) t pde (min) clk cke command nop notes: 1. precharge command (pre or pall) should be asserted if any bank is active prior to self-refresh entry command (self). 2. the self-refresh exit command (selfx) is latched after t pde (min). it is recommended to apply nop command in conjunction with cke. it is also recommended to apply minimum of 4 clocks to stabilize external clock prior to selfx command. 3. either nop or desl command can be used during t rc period. self don?t care srex command nop 2 nop 3 1 timing diagram e 17 : mode register set timing clk command address mrs nop or desl mode row adress actv note: the mode register set command (mrs) should be only issued after all banks have been precharged. i mrd (min 2 clocks)
42 mb81117822a-125/-100/-84/-67 n package dimensions 44 pin, plastic tsop(ii) (fpt-44p-m18) (.045.002) 1.150.05 lead no. 0.10(.004) max 0.40(.016) max 0.15(.006) 0.25(.010) details of "a" part (.005.002) 0.1250.05 (.400.004) 10.160.10 (.463.008) 11.760.20 (.424.008) 10.760.20 (.020.004) 0.500.10 (stand off) 0.05(.002)min 0.10(.004) typ. 0.80(.031) ref. 16.80(.661) * 0.13(.005) m (.012.004) 0.300.10 (.725.004) 18.410.10 index "a" 22 1 23 44 1995 fujitsu limited f44025s-1c-1 c * resin protrusion. (each side:.006(0.15)max.) dimensions in mm ( inches) (mounting height) (stand off height)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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